URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Rev 29

Rev	Log message	Author	Age	Path
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5547d 04h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
17	Updated header with SVN info	olivier.girard	5572d 23h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5607d 23h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim