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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim_c] - Rev 219

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Rev	Log message	Author	Age	Path
207	Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin)	olivier.girard	3340d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
202	Add DMA interface support + LINT cleanup	olivier.girard	3451d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
200	Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.	olivier.girard	3612d 10h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
192	Number of supported IRQs is now configurable to 14 (default), 30 or 62.	olivier.girard	4012d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4525d 10h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4603d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4615d 21h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
122	Add coverage report generation (NCVERILOG only) Add support for the ISIM Xilinx simulator.	olivier.girard	4816d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	5035d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	5137d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c

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