URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [rtlsim.sh] - Rev 36

Rev	Log message	Author	Age	Path
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5451d 16h	/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
17	Updated header with SVN info	olivier.girard	5598d 13h	/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5633d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh