URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [template.x] - Rev 192

Rev	Log message	Author	Age	Path
192	Number of supported IRQs is now configurable to 14 (default), 30 or 62.	olivier.girard	3999d 16h	/openmsp430/trunk/core/sim/rtl_sim/bin/template.x
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4634d 15h	/openmsp430/trunk/core/sim/rtl_sim/bin/template.x
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4941d 15h	/openmsp430/trunk/core/sim/rtl_sim/bin/template.def
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5448d 18h	/openmsp430/trunk/core/sim/rtl_sim/bin/template.def
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5630d 14h	/openmsp430/trunk/core/sim/rtl_sim/bin/template.def