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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Rev 166

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4618d 19h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4925d 19h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4981d 17h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
95 Update some test patterns for the additional simulator supports. olivier.girard 5010d 19h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5190d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5398d 16h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5432d 21h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
19 added SVN property for keywords olivier.girard 5579d 18h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
18 Updated headers with SVN info olivier.girard 5579d 18h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5614d 18h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v

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