URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Rev 80

Rev	Log message	Author	Age	Path
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5025d 16h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
58	Update the debug hardware breakpoint verification patterns to reflect the latest design updates.	olivier.girard	5233d 13h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5267d 18h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
19	added SVN property for keywords	olivier.girard	5414d 14h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
18	Updated headers with SVN info	olivier.girard	5414d 14h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5449d 15h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v