URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_onoff.v] - Rev 172

Rev	Log message	Author	Age	Path
154	The serial debug interface now supports the I2C protocol (in addition to the UART)	olivier.girard	4402d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4609d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4916d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4972d 19h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v