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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Rev 192

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180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4434d 05h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4774d 06h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 5081d 06h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
95 Update some test patterns for the additional simulator supports. olivier.girard 5166d 06h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5259d 07h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
19 added SVN property for keywords olivier.girard 5735d 05h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
18 Updated headers with SVN info olivier.girard 5735d 05h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5770d 05h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v

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