URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 103

Rev	Log message	Author	Age	Path
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	5161d 17h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
67	Added 16x16 Hardware Multiplier.	olivier.girard	5524d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5592d 12h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5713d 15h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
19	added SVN property for keywords	olivier.girard	5739d 10h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
18	Updated headers with SVN info	olivier.girard	5739d 10h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5774d 10h	/openmsp430/trunk/core/sim/rtl_sim/src/submit.f