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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 137

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134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4639d 04h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4946d 04h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 5002d 03h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 5017d 04h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 5022d 10h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
67 Added 16x16 Hardware Multiplier. olivier.girard 5385d 13h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5453d 06h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5574d 08h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
19 added SVN property for keywords olivier.girard 5600d 03h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
18 Updated headers with SVN info olivier.girard 5600d 03h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5635d 04h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f

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