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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 62

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34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5425d 14h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5546d 17h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
19 added SVN property for keywords olivier.girard 5572d 11h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
18 Updated headers with SVN info olivier.girard 5572d 12h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5607d 12h /openmsp430/trunk/core/sim/rtl_sim/src/submit.f

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