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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Rev 115

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111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4942d 06h /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl
56 Update Design Compiler Synthesis scripts. olivier.girard 5419d 10h /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5631d 05h /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl

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