URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [openMSP430_fpga.prj] - Rev 121

Rev	Log message	Author	Age	Path
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4942d 04h	/openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj
68	Update synthesis scripts with the hardware multiplier support.	olivier.girard	5381d 12h	/openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj
62	Add Xilinx synthesis environment for size&speed analysis.	olivier.girard	5402d 14h	/openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj