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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [xst_verilog_spartan6.opt] - Rev 169

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62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5382d 05h /openmsp430/trunk/core/synthesis/xilinx/xst_verilog_spartan6.opt

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