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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 221

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Rev Log message Author Age Path
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 3030d 02h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
136 Update all FPGA projects with the latest core version. olivier.girard 4639d 02h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4946d 03h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5002d 01h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 5017d 02h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5385d 03h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
39 Update FPGA projects with new openMSP430 core. olivier.girard 5453d 02h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
29 Add Altera Cyclone II FPGA project example. olivier.girard 5455d 03h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f

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