OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 221

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
221 Move old Altera-DE1 project to the OBSOLETE directory.
Create new Altera-DE0-Nano-SoC project, also containing a small demo of the openGFX430 graphic controller.		 olivier.girard 3031d 05h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
136 Update all FPGA projects with the latest core version. olivier.girard 4640d 06h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4947d 06h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5003d 04h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 5018d 06h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5386d 07h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
39 Update FPGA projects with new openMSP430 core. olivier.girard 5454d 05h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f
29 Add Altera Cyclone II FPGA project example. olivier.girard 5456d 07h /openmsp430/trunk/fpga/OBSOLETE/altera_de1_board/sim/rtl_sim/src/submit.f

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.