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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Rev 222

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136 Update all FPGA projects with the latest core version. olivier.girard 4647d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4954d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5010d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5029d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 5035d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5039d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5120d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog/tb_openMSP430_fpga.v

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