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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [dac_spi_if.v] - Rev 222

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111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4947d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5003d 05h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5022d 08h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5113d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v

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