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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openMSP430_fpga.v] - Rev 205

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202 Add DMA interface support + LINT cleanup olivier.girard 3641d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4630d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
136 Update all FPGA projects with the latest core version. olivier.girard 4837d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 5144d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5200d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5219d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 5307d 15h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 5310d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5310d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v

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