OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_frontend.v] - Rev 202

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3769d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
193 Update FPGA projects with latest core RTL changes. olivier.girard 4330d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
136 Update all FPGA projects with the latest core version. olivier.girard 4965d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 5272d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 5327d 22h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 5343d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5347d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 5361d 01h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
85 Diverse RTL cosmetic updates. olivier.girard 5384d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5438d 07h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.