URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Rev 132

Rev	Log message	Author	Age	Path
112	Modified comment.	olivier.girard	4940d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4941d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4997d 21h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	5016d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5108d 06h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v