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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3440d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
193 Update FPGA projects with latest core RTL changes. olivier.girard 4001d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
181 Update with latest oMSP Core version. olivier.girard 4296d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4429d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
136 Update all FPGA projects with the latest core version. olivier.girard 4636d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4943d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4999d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5110d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v

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