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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA.v] - Rev 204

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Rev Log message Author Age Path
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3302d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
136 Update all FPGA projects with the latest core version. olivier.girard 4505d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4812d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4868d 00h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4887d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4978d 09h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v

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