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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [smartgen/] [dmem_128B.v] - Rev 191

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81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 5120d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5121d 05h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v

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