URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [smartgen/] [dmem_128B.v] - Rev 191

Rev	Log message	Author	Age	Path
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	5120d 21h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5121d 05h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/dmem_128B.v