URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 227

Rev	Log message	Author	Age	Path
155	Update FPGA projects with the latest openMSP430 verilog code.	olivier.girard	4430d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
136	Update all FPGA projects with the latest core version.	olivier.girard	4637d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4944d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	5000d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	5015d 17h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5111d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src/submit.f