URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] [design_files.v] - Rev 211

Rev	Log message	Author	Age	Path
155	Update FPGA projects with the latest openMSP430 verilog code.	olivier.girard	4440d 06h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
136	Update all FPGA projects with the latest core version.	olivier.girard	4647d 06h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4954d 07h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	5117d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5120d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel/design_files.v