URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [omsp_clock_module.v] - Rev 208

Rev	Log message	Author	Age	Path
205	Thanks again to Johan W. good feedback, the following updates are implemented: - Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment. - Update oscillators enable generation to relax a critical timing paths in the ASIC version. - Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).	olivier.girard	3422d 03h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
202	Add DMA interface support + LINT cleanup	olivier.girard	3436d 03h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
181	Update with latest oMSP Core version.	olivier.girard	4292d 03h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
157	Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come)....	olivier.girard	4425d 03h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v