URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Rev 199

Rev	Log message	Author	Age	Path
193	Update FPGA projects with latest core RTL changes.	olivier.girard	3978d 16h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
181	Update with latest oMSP Core version.	olivier.girard	4273d 14h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
171	Update in order to add Hardware breakpoint support. Hardware breakpoint are here only added for development purpose in order to add multi-core features as well as software & hardware breakpoint support to the GDB-Proxy.	olivier.girard	4333d 13h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
167	Update LX9 Microboard FPGA example. It now includes a dual-core oMSP system with a shared 16kB program memory. Each core has its own 2kB data memory and an additional 2kB shared data memory.	olivier.girard	4354d 15h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
157	Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come)....	olivier.girard	4406d 14h	/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v