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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [msp_debug.v] - Rev 222

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136 Update all FPGA projects with the latest core version. olivier.girard 4644d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4951d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5026d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim
olivier.girard 5036d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5468d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5579d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
16 Updated header with SVN info olivier.girard 5605d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5640d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v

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