URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Rev 143

Rev	Log message	Author	Age	Path
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4586d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
136	Update all FPGA projects with the latest core version.	olivier.girard	4634d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4941d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
37		olivier.girard	5448d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5459d 04h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
16	Updated header with SVN info	olivier.girard	5595d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5630d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v