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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [registers.v] - Rev 222

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143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4595d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
136 Update all FPGA projects with the latest core version. olivier.girard 4643d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4950d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
37 olivier.girard 5457d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5468d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
16 Updated header with SVN info olivier.girard 5604d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5639d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/registers.v

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