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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [timescale.v] - Rev 182

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104 Update all FPGA example projects with the latest RTL version. olivier.girard 4999d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/bench/verilog/timescale.v

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