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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [ram_8x512_hi.v] - Rev 109

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28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5447d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5619d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v

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