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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [rom_8x2k_hi.sym] - Rev 190

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28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5440d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5612d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.sym

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