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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [driver_7segment.v] - Rev 111

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111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4780d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4834d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4855d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5297d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5408d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
16 Updated header with SVN info olivier.girard 5434d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5469d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v

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