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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_hwbrk.v] - Rev 102

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59 Update the FPGA projects with the latest core design updates. olivier.girard 5427d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
37 olivier.girard 5461d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5461d 10h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.
olivier.girard 5461d 11h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5582d 13h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
17 Updated header with SVN info olivier.girard 5608d 08h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5643d 08h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v

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