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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA.v] - Rev 104

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104 Update all FPGA example projects with the latest RTL version. olivier.girard 5013d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v
37 olivier.girard 5445d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5445d 11h /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5445d 12h /openmsp430/trunk/core/rtl/verilog/periph/timerA.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5566d 13h /openmsp430/trunk/core/rtl/verilog/periph/timerA.v
17 Updated header with SVN info olivier.girard 5592d 09h /openmsp430/trunk/core/rtl/verilog/periph/timerA.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5627d 09h /openmsp430/trunk/core/rtl/verilog/periph/timerA.v

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