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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA_defines.v] - Rev 136

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136 Update all FPGA projects with the latest core version. olivier.girard 4634d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4996d 06h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA_defines.v

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