URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 94

Rev	Log message	Author	Age	Path
85	Diverse RTL cosmetic updates.	olivier.girard	5033d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5360d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
37		olivier.girard	5428d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5439d 05h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5439d 05h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5550d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
16	Updated header with SVN info	olivier.girard	5575d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5610d 20h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f