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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [software/] [leds/] [makefile] - Rev 174

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4402d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4561d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4972d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5355d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5433d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5605d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/makefile

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