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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_cfgr.v] - Rev 855

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795 Created or1200_rel3 branch from rev 794 olof 4442d 22h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_cfgr.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5044d 17h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_cfgr.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5095d 01h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_cfgr.v
141 added OpenRISC version rel3 marcus.erlandsson 5106d 05h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_cfgr.v
10 or1200 added from or1k subversion repository unneback 5507d 09h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_cfgr.v

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