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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Rev 795

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4588d 00h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_32x32.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5179d 10h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_32x32.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5189d 19h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_32x32.v
141	added OpenRISC version rel3	marcus.erlandsson	5251d 07h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_32x32.v
10	or1200 added from or1k subversion repository	unneback	5652d 11h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_32x32.v