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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_fpu_post_norm_addsub.v] - Rev 795

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4588d 02h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_fpu_post_norm_addsub.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5177d 02h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_fpu_post_norm_addsub.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5189d 21h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_fpu_post_norm_addsub.v