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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_genpc.v] - Rev 818

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4608d 01h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5197d 01h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5199d 10h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5209d 20h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5260d 03h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
141	added OpenRISC version rel3	marcus.erlandsson	5271d 08h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v
10	or1200 added from or1k subversion repository	unneback	5672d 11h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_genpc.v