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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_spram_1024x32.v] - Rev 858

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795 Created or1200_rel3 branch from rev 794 olof 4631d 09h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_spram_1024x32.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5222d 19h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_spram_1024x32.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5233d 04h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_spram_1024x32.v
142 added OpenRISC version rel3 marcus.erlandsson 5294d 16h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_spram_1024x32.v
10 or1200 added from or1k subversion repository unneback 5695d 20h /openrisc/branches/or1200_rel3/rtl/verilog/or1200_spram_1024x32.v

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