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[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_top.v] - Rev 818

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Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4615d 19h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
679	Allow setting the boot address as an external parameter. If no parameter is used, the value from OR1200_BOOT_ADR will be used Signed-off-by: Olof Kindgren <olof@opencores.org> Acked-by: Julius Baxter <juliusbaxter@gmail.com>	olof	4669d 20h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
481	OR1200 Update. RTL and spec.	julius	5076d 11h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5204d 20h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5217d 14h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5267d 22h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
142	added OpenRISC version rel3	marcus.erlandsson	5279d 02h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v
10	or1200 added from or1k subversion repository	unneback	5680d 06h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_top.v

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