URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or1k/] [spr-defs.h] - Rev 347

Rev	Log message	Author	Age	Path
347	Tagging the 0.5.0rc1 candidate release of Or1ksim.	jeremybennett	5051d 16h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
239	or1ksim fixed SPR_VR_RESV value	julius	5083d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
233	New softfloat FPU and testfloat sw for or1ksim	julius	5087d 05h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5090d 10h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
224	Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg.	jeremybennett	5090d 18h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5191d 10h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5521d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or1k/spr-defs.h