URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [cpu/] [or1k/] [sprs.c] - Rev 580

Rev	Log message	Author	Age	Path
509	Tagging the 0.5.0rc3 release of Or1ksim	jeremybennett	4834d 03h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4835d 02h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4963d 12h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
432	Updates to handle interrupts correctly.	jeremybennett	4967d 21h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	4970d 18h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5085d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5157d 22h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5517d 04h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu/or1k/sprs.c