OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [peripheral/] [memory.c] - Rev 612

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
509 Tagging the 0.5.0rc3 release of Or1ksim jeremybennett 4845d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/peripheral/memory.c
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4911d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/peripheral/memory.c
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4993d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/peripheral/memory.c
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5097d 09h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/peripheral/memory.c
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5528d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc3/peripheral/memory.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.