Rev |
Log message |
Author |
Age |
Path |
509 |
Tagging the 0.5.0rc3 release of Or1ksim |
jeremybennett |
4889d 19h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4982d 19h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
458 |
or1ksim testsuite updates |
julius |
4983d 23h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
4992d 13h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
5022d 10h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
432 |
Updates to handle interrupts correctly. |
jeremybennett |
5023d 14h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
346 |
Changes to support Or1ksim 0.5.0rc1
Top level changes:
* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
Changes in testsuite:
* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.
Changes in testsuite/test-code-or1k:
* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1. |
jeremybennett |
5102d 17h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
235 |
Removed support for old OpenRISC JTAG Remote Protocol. |
jeremybennett |
5136d 17h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
234 |
Minor tidy ups. DOS end of line chars fixed. |
jeremybennett |
5137d 19h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
220 |
Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. |
jeremybennett |
5148d 10h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
124 |
Overflow handling now in line with architecture manual. Tests added. |
jeremybennett |
5186d 10h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
123 |
Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. |
jeremybennett |
5186d 14h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
122 |
Added l.ror and l.rori with associated tests. |
jeremybennett |
5187d 10h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
121 |
Adds exception handling to l.jalr and l.jr. Adds appropriate tests. |
jeremybennett |
5187d 11h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
118 |
New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. |
jeremybennett |
5188d 08h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
116 |
Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. |
jeremybennett |
5190d 11h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
115 |
Added support for l.fl1 and tests for l.ff1 and l.fl1 |
jeremybennett |
5191d 11h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
114 |
l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. |
jeremybennett |
5191d 12h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
112 |
Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. |
jeremybennett |
5192d 11h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |
107 |
New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. |
jeremybennett |
5195d 11h |
/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/testsuite/ChangeLog |